FPGA Quality Assurance Engineer | Crofton, MD

Detailed Information

  • Location: Linthicum Heights, MD

  • Company: Rampart Communications

in information security. This role is for an FPGA Quality Assurance Engineer focused on ensuring coding standards and quality compliance as well as developing robust testing suites to validate complex digital communications systems against golden reference models.

The work will include testing in simulation as well as hardware-in-the-loop verification using FPGA hardware in conjunction with analog front-ends. For simulation, the role will require the use of third-party EDA simulation tools utilizing bus functional models (BFMs) and advanced testing frameworks such as UVM/UVVM along with vendor provided verification IP (VIP) to validate HDL models against MATLAB golden models. Responsibilities

Design and maintain testing infrastructure for Rampart's FPGA development organization Develop bus functional models (BFMs) to aid in simulation and reduce code duplication Create test suites leveraging industry standard testing frameworks (UVM/UVVM or equivalent) Work intimately with FPGA Design Engineers and DSP Engineers to troubleshoot test failures and to aid in creating new tests Make use of existing options for connecting test suites to MATLAB golden reference models to validate HDL Leverage EDA simulation tool features to create testing metrics such as code coverage percentage, failure reports, etc.

Create hardware-in-the-loop tests to validate that designs work in hardware Minimum

Required Qualifications Experience performing FPGA design verification using System Verilog with OVM/UVM or VHDL with UVVM/OSVVM Strong background in Cadence Xcelium or Incisive simulators Proven ability to work with FPGA module developers providing feedback to address discovered issues Ability to work in a Linux only environment Experience using VPI (Verilog/System Verilog) or FLI (VHDL) to interface with C/C++ golden models Experience using Tcl to automate EDA tools such as Cadence Xcelium, Model Sim, Vivado, Quartus, etc.

Experience writing and taking action on test plans for FPGA/ASIC designs Expert in common problem areas of FPGA designs such as CDC, HDL language edge cases, and bugs in standard protocols (AXI, AXIS, AMBA, etc.

) Preferred Skills and Experience Experience using formal verification tools ASIC verification experience Experience testing with hardware-in-the-loop Experience using software development life cycle (SDLC) principles for testing Experience using Git for revision control Vivado and/or Quartus expertise Experience using Team City (preferred) or Jenkins for CI/CD Experience using Python for task automation Nice to Have Digital signal processing background C/C++ development experience MATLAB HDL Verifier and FPGA-in-the-Loop experience Other Requirements Willing to work onsite at our Linthicum Heights, Maryland, office U.

S. Citizenship is required for all positions COVID-19 Guidelines The health and safety of our community is the highest priority. As such, Rampart Communications is requiring all employees, interns and contractors to be fully vaccinated with an FDA authorized and/or approved COVID-19 vaccine as a condition of employment. Requests for reasonable accommodations for medical, religious, or other reasons will be considered in accordance with applicable law.

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