ASIC Design Engineer | Madison, WI

Detailed Information

  • Location: Madison, WI

  • Company: Google

largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart

so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. The US base salary range for this full-time position is $124,000-$182,000 bonus equity benefits.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during

the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

Learn more about benefits at Google. Minimum qualifications: Bachelor's degree or equivalent practical experience. Experience in hardware (e. g. Verilog or System Verilog) or programming language (e. g. C , Python, Go, etc. ). Preferred qualifications: Master's degree or Ph D. Experience with computer arithmetic and with performance modeling, with highly pipelined designs, and with multiple-clock-domain designs. Experience applying engineering best practices (e. g. code review, testing, and refactoring).

Experience applying computer architecture principles to solve open-ended problems. Knowledge of processor design, accelerators, or memory hierarchies. Knowledge of machine learning algorithms. - Understand the overall application of the chip, proposing, and developing improvements in overall design. - Design and document one or more blocks of an ASIC, including functionality and timing. - Work closely with software teams on functionality, interfaces, and documentation. Requisition #: 139843660091925190pca3lyuhf

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