Location: Phoenix, AZ
Company: Intel
packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. Within TD, ATTD designs and delivers packaging and test solutions for Intel products and foundry customers that enable world-class technologies leveraging an increasing heterogenous chip architecture.
About the Role: The Product Package Architect is responsible for the package architecture definition for the next generation of Intel products and the long term roadmap for the next generation advanced packaging needs to meet the product requirements. The package Architect will work with the ATTD pathfinding team to define the development and alignment
of major new packaging features and align to product timelines. The position will manage BU product needs and drive new technologies such as multi high die stacking architecture, memory technologies integration(DDR, LPDDR, HBM, ADM.), power delivery (Top side, on package voltage regulation ), Substrate materials need, IO chiplet solutions, FLI and SLI pitch scaling.
The Product architect will regularly work with ATTD's Core competency teams as well as business unit design and Si/Pi teams and engineering group design teams to drive detailed studies of proposed product features in advance of product alignment. Responsibilities will include: Drive the package architecture definition and
packaging technologies needed for next generation Intel products. Develop long-term roadmaps for these features to minimize cost and maximize re-use across product lines Align the assembly TD required to enable these features through pathfinding decision forums Work with business unit and engineering team architects to create straw-man proposals for new packaging, assembly, and test features Coordinate multi-disciplinary, multi-division teams to evaluate and evolve these features until they provide a clear value proposition for Intel or are documented and dropped.
Coordinate alignment of these features to product families in ensuring any required building blocks reach maturity on the required timelines Coordinate demonstrations of new features using test chips and custom test packaging Qualifications Required Experience/skills: Experience in electronics packaging development Familiarity with microprocessor power integrity, signal integrity, IC packaging thermal and IC packing mechanical simulations, the data they produce, and the way they impact product and technology development decision making Preferred Experience/skills: Direct working experience in one or more of the following disciplines: power integrity, signal integrity, analog or digital circuit design, packaging, or IP design Familiarity with die and package layout tools including the ability to view and interpret designs Basic understanding of microelectronics and fundamental computer architecture concepts Familiarity with typical assembly and test flows Qualifications MS or Ph D Degree in electrical, computer, mechanical, or thermal engineering or a closely related discipline 15+ years of experience in the semiconductor industry Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Other Locations US, OR, Hillsboro; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, interaction, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, interactionual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $211,730.00-$339,050.00Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks.
For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Requisition #: JR0254552pca3lyuhf
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