Location: Austin, TX
Company: Intel
floor planning. Clock tree synthesis. RTL to gate level netlist generation through synthesis, placement, clock tree synthesis and route flows. Static timing analysis and convergence flows Validation of physical design including timing, electrical rules, DRC/LVS, Noise, electro migration checks.
Formal equivalence verification. Scripting to automate tasks and improve debug efficiency. Oversee definition, design, verification, and documentation for So C (System on a Chip) development. Determine architecture design, logic design, and system simulation. Define module interfaces/formats for simulation. Perform Logic design for integration of cell libraries, functional units and subsystems
into So C full chip designs, Register Transfer Level coding, and simulation for So Cs. Contribute to the development of multidimensional designs involving the layout of complex integrated circuits.
Perform all aspects of the So C design flow from high level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Review vendor capability to support development. The ideal candidate will also exhibit behavioral traits that indicate: Works well in a team and is productive under aggressive schedules. Written and verbal communication skills. Self-motivation and good organizational skills. Qualifications You must possess the below minimum
qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications (must haves): Candidate must have a bachelor's degree in computer or electrical Engineering and 6+ years of experience - OR - a master's degree in computer or electrical Engineering and 5+ years' experience. Preferred Qualifications (good to have): 4+ yrs. of exp in two or more of the following Physical design with synthesis and APR flows Chip physical design verification including FEV, timing, electrical rules, DRC/LVS, Noise, RVTools such as Fusion, Genus, Innovus, Prime Time, PTSI, Conformal, LEC, Redhawk, Caliber and Duet TCL and Perl coding Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products.
From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, interaction, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, interactionual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0251095pca3lyuhf
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