Location: San Jose, CA
environments and test plans Work closely with design engineers to develop test benches and test plans to meet coverage goals Participate in selecting best in class 3rd party protocol verification IPHelp enhance the overall DV methodology by analyzing 3rd party verification tools Debug failures in simulation and collaborate with designers in identifying root-cause issues Develop a tests that will help achieve functional safety goals that meet ISO26262 compliance Work with the systems and software teams on emulation platforms Participate in the bring-up and debug of the device prototype Provide support to the Product Engineering team to meet all validation and qualification goals for the product
MINIMUM QUALIFICATIONS BSEE/BSCE/BSCS5 years of industry experience in design verification Experience with test planning, test bench architecture and assertions Constrained random verification experience with System Verilog using UVMCoverage driven verification (code/functional/assertion coverage)Strong programming skills in C/C++ and scripting experience with Python/Tcl/Perl
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